Commit 0c59bb07 authored by sam's avatar sam

modify Sample/sys/main.c code format

parent adf5a130
...@@ -50,8 +50,9 @@ void DemoAPI_AdjustApllDivider(void) ...@@ -50,8 +50,9 @@ void DemoAPI_AdjustApllDivider(void)
{ {
for(j=u32SysDiv0; j<8;j=j+1) for(j=u32SysDiv0; j<8;j=j+1)
{ {
outp32(REG_CLKDIV0, (inp32(REG_CLKDIV0) & ~0xF07) | outp32(REG_CLKDIV0,
((i<<8) | j)); (inp32(REG_CLKDIV0) & ~0xF07) |
((i<<8) | j));
DBG_PRINTF("SYS divider1 %d, divider0 %d\n", i, j); DBG_PRINTF("SYS divider1 %d, divider0 %d\n", i, j);
} }
} }
...@@ -124,40 +125,61 @@ int main() ...@@ -124,40 +125,61 @@ int main()
u32Item = sysGetChar(); u32Item = sysGetChar();
switch(u32Item) switch(u32Item)
{ {
case '1': DemoAPI_UART(); break; //OK-sysprintf case '1':
case '2': DemoAPI_Timer0(); break; DemoAPI_UART();
case '3': DemoAPI_Timer1(); break; break; //OK-sysprintf
case '4': DemoAPI_WDT(); break; case '2':
case '5': DemoAPI_Cache(FALSE); break; DemoAPI_Timer0();
case '6': DemoAPI_Cache(TRUE); break; break;
case '7': DemoAPI_AIC(); break; case '3':
case '8': sysPowerDownPLL(eSYS_UPLL, FALSE); DemoAPI_Timer1();
sysPowerDownPLL(eSYS_APLL, FALSE); break;
DemoAPI_CLK(); break; case '4':
case '9': sysPowerDownPLL(eSYS_UPLL, FALSE); DemoAPI_WDT();
sysPowerDownPLL(eSYS_APLL, FALSE); break;
DemoAPI_CLKRandom(); case '5':
break; DemoAPI_Cache(FALSE);
case 'a': Demo_PowerDownWakeUp(); break;
break; case '6':
case 'b': DemoAPI_HUART(); DemoAPI_Cache(TRUE);
break; break;
case '7':
case 'c': DemoAPI_SetSystemDivider(); DemoAPI_AIC();
break; break;
case 'd': sysSetSystemClock(eSYS_EXT, //E_SYS_SRC_CLK eSrcClk, case '8':
sysPowerDownPLL(eSYS_UPLL, FALSE);
sysPowerDownPLL(eSYS_APLL, FALSE);
DemoAPI_CLK();
break;
case '9':
sysPowerDownPLL(eSYS_UPLL, FALSE);
sysPowerDownPLL(eSYS_APLL, FALSE);
DemoAPI_CLKRandom();
break;
case 'a':
Demo_PowerDownWakeUp();
break;
case 'b':
DemoAPI_HUART();
break;
case 'c':
DemoAPI_SetSystemDivider();
break;
case 'd':
sysSetSystemClock(eSYS_EXT, //E_SYS_SRC_CLK eSrcClk,
u32ExtFreq, //UINT32 u32PllKHz/EXT, u32ExtFreq, //UINT32 u32PllKHz/EXT,
u32ExtFreq, //UINT32 u32SysKHz, u32ExtFreq, //UINT32 u32SysKHz,
u32ExtFreq/2, //UINT32 u32CpuKHz, u32ExtFreq/2, //UINT32 u32CpuKHz,
u32ExtFreq/2, //UINT32 u32HclkKHz, u32ExtFreq/2, //UINT32 u32HclkKHz,
u32ExtFreq/4); //UINT32 u32ApbKHz u32ExtFreq/4); //UINT32 u32ApbKHz
sysClockDivSwitchStart(7); /* Max system divider */
sysClockDivSwitchStart(7); /* Max system divider */ sysPowerDownPLL(eSYS_UPLL, TRUE);
sysPowerDownPLL(eSYS_UPLL, TRUE); sysPowerDownPLL(eSYS_APLL, TRUE);
sysPowerDownPLL(eSYS_APLL, TRUE); case 'Q':
case 'Q': break; break;
case 'q': break; case 'q':
break;
} }
}while((u32Item!= 'q') || (u32Item!= 'Q')); }while((u32Item!= 'q') || (u32Item!= 'Q'));
return 0; return 0;
} /* end main */ } /* end main */
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